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Digital Analog Design

Official website will be available soon. For more information, contact bclim At stanford dot edu

DaVE tool can be downloaded at Stanford's VLSI group website


"Digital Analog Design" is a design flow to improve the design/verification productivity of mixed-signal system-on-chips (MS SoCs) developed by VLSI research group at Stanford university. Our mission is to formalize design & verification flow and develop relevant tools of mixed-signal system-on-chips.
Today, unlike traditional A-D/D-A systems, the analog and digital subsystems in MS SoCs are tightly coupled. The big challenge in validating such SoCs is that they should be validated together, but their validation approaches are completely different. Unfortunately, MS SoCs are already too complicated to validate by running mixed-mode simulations (i.e. fast SPICE simulators + event-driven digital simulators).
Our method is to partition a mixed-signal chip into smaller cells and provide many abstraction levels for each cell like digital standard cells. Each analog cell has the following components:
  • Functional model in SystemVerilog
  • Circuit netlist and testbenches
  • Physical layout.
Then, designers use each component for different purposes in chip validation. The functional model will be used for functional validation at chip-level and enable regression tests. The transistor-level implementation of the component is verified for electrical-rule checks using circuit simulators. The layout is for generating a chip. This approach will provide better encapsulation of analog functions, and be fully compatible with the existing digital verification tools. This will eventually simplify the design/verification of MS-SoCs.

Selected Publications

  • B. C. Lim and M. Horowitz, ""Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models," IEEE Transactions on Circuits and Systems — I: Regular Papers, Jan. 2016. [Link]
  • B. C. Lim, J. Jang, J. Mao, J. Kim, and M. Horowitz, “Digital Analog Design: Enabling Mixed-Signal System Validation,” IEEE design and test magazine, Feb. 2015. [Link]
  • B. C. Lim, Model Validation of Mixed-Signal Systems, Ph.D. thesis, Stanford university, 2012. [Link]
  • B. C. Lim, J. Kim and M. Horowitz, “An Efficient Test Vector Generation for Checking Analog/Mixed-Signal Functional Models,” ACM/IEEE Design Automation Conference (DAC), June 2010. [Link]
  • M. Horowitz, M. Jeeradit, F. Lau, S. Liao, B. C. Lim, and J. Mao, “Fortifying analog models with equivalence checking and coverage analysis,” ACM/IEEE Design Automation Conference (DAC), June 2010. [Link]
  • J. Kim, M. Jeeradit, B. C. Lim and M. Horowitz, “Leveraging Designer’s Intent: A Path Toward Simpler Analog CAD Tools (invited paper),” IEEE 2009 Custom Integrated Circuit Conference, Sept. 2009. [Link]