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Dr. Lim is an engineering research associate in the Department of Electrical Engineering, Stanford University. Under the supervision of Prof. Mark Horowitz, he has been conducting research on mixed-signal circuit design and methodologies to improve the productivity of mixed-signal SoC design and validation. He received his PhD in Electrical Engineering from Stanford University, in 2012. Before joining the group, from 2003~2007, he had worked on developing various analog IPs/Chips such as high-speed link, PLL(DLL), Image processor, and so on for LG Electronics Inc.

Research Interest

My research interests include:

  • Improving the productivity of of mixed-signal SoC design/validation
    • Efficient modeling of analog/mixed-signal circuits in SystemVerilog
    • Model equivalence checking
    • Model generation
    • Hardware emulation of mixed-signal SoCs
  • Mixed-signal circuit design

For now, my main research focus is on validating mixed-signal SoCs using analog functional models and developing relevant tools. 

Curriculum Vitae

Click here.